The present invention relates to image reject mixer circuit arrangements and in particular, although not exclusively, to image reject mixer circuit arrangements suitable for integrated circuit implementation in radio receivers for radio telephones.
Image reject mixers are preferred to conventional mixers for use in miniaturized radio receiver applications because image reject filters required by the conventional mixers tend to be both bulky and expensive. However, known image reject mixer have tended to demand significant current levels, in comparison with conventional mixers, because of the larger number of circuit blocks involved, which are generally connected in cascade. This is undesirable in battery powered radio equipment in that their use provides unwanted drain on the battery""s charge, of particular significance in radiotelephones where battery replacement or re-charging frequency is desired to be low. UK Patent Application numbers 9724435.4 and 9700485.7 disclose the cascode connection of certain image reject mixer arrangement circuit blocks to reduce overall current consumption.
In accordance with a first aspect of the present invention, there is provided an image reject mixer circuit arrangement comprising input means to receive an input signal and to provide on each of first and second paths differential current signals derived from the input signal, the first and second paths each including a current mode mixer core arranged to mix the differential current signals with respective ones of In-phase and Quadrature local oscillator signals, and at least one of the first and second paths including phase shifter means to introduce a phase shift of the signal in the respective path compared to a signal in the opposite path, and current mode combiner means arranged to combine the signals from the first and second paths to provide an output signal.
Each of said first and second paths may include a phase shifter circuit.
Preferably, transistors forming part of the transconductor means are connected in cascode with transistors forming part of the quadrature mixer means. Further, transistors forming part of the quadrature mixer means are preferably connected in cascode with transistors forming part of the combiner means.
Said input means may comprise a low voltage headroom transconductor having differential inputs and a relatively low gain and a high gain pre-amplifier arranged to receive an or the single-ended input signal and to provide amplified and phase-split signals therefrom to the differential inputs of the transconductor means.
In accordance with a second aspect of the present invention, an image reject mixer circuit arrangement comprises transconductor means, quadrature mixer means, phase shifter means and combiner means connected in series across a voltage supply, the transconductor means providing first and second current signals on first and second paths respectively, each of the first and second current signals being representative of an input signal, to respective ones of an in-phase and a quadrature mixer core means forming said quadrature mixer means, the mixer core means providing current signals on their respective path via the phase shifter means to the combiner means which sums the current signals to provide an output signal.
Where the transconductor means comprises a low voltage headroom transconductor having differential inputs and a relatively low gain, the arrangement may further comprise a high gain pre-amplifier arranged to receive an or the single-ended input signal and to provide amplified and phase-split signals therefrom to the different inputs of the transconductor means.
Preferably, any such image reject mixer arrangement is implemented as an integrated circuit, which may be the radioreceiver IC of a radiotelephone.